In
this section, Video-Mode Timing examples are described to show how to
generate video-mode timing signals from DSI data packets and DSI
clock.
Hsync,
Vsync and Pixel clock signals need to be issued periodically and
continuously in Video mode. Hsync signal should be generated after
detecting ECC byte of HS sync packet. Hsync pulse width is defined by
user system in this case; i.e. with sync event method ( See MIPI DSI
specification, section 8.11.3 Non-Burst Mode with Sync Events).
DE
timing “HACT” is determined by HBP and HFP, and specifies an
effective display area. The duration of HACT shall be multiple of
pixel clock period and HACT is determined by the number of horizontal
pixel count. Since the end of DE timing is specified after detecting
ECC of HFP packet, the start of DE timing should be delayed by 6
bytes including two checksum bytes of RGB Long packet. RGB long
packet header and following 6 bytes data are included in HBP
duration. And 4 bytes of HS short packet is included in HFP duration.
Figure
3 Display Timing Generation from DSI Byte Stream in Non-burst Mode
Figure
4 shows Display timing generation from DSI byte stream in Burst Mode.
The main difference between Burst Mode and Non-burst Mode is
existence of BLLP after transmitting compressed RGB data. To keep
Hsync signal synchronous, the duration of BLLP shall be multiple of
pixel clock period. In this case, HACT also represents effective
display horizontal area. DE timing is different from Non-burst Mode
case. The end timing of DE is the same as Non-burst Mode, but the
start timing may be defined to the first byte of RGB payload data,
because HACT time can be specified to adjust BLLP duration.
Therefore, Host shall have the capability of adjusting BLLP time
including EoT and SoT.
Figure
4 Display Timing Generation from DSI Byte Stream in Burst Mode
by
MIPI
Alliance
Display Working Group
Display Working Group
TEST
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