Welcome to MFG(Mipi Function Generator) World: Burst Communication Example

Figure2 shows DSI Video Mode Interface Timing of Burst Communication with sync event. The generating method of Hsync and DE follows the same procedure of Non-burst Communication Example. In this case, there are two options for generating Pixel Clock. One is generated by the divided down DSI Clock and the other is the divided down Internal Clock in a peripheral.

When Internal Clock is used, Internal Clock or at least Pixel Clock should be synchronous with Hsync, otherwise the display data may not be shown on a display properly. DSI Clock may enter Low Power Mode during the BLLP time of DSI data lane as long as Internal Clock is operating. To achieve Burst Communication, line buffers or similar memories may be used. In this example two line buffers are used; Write Line Buffer and Read Line Buffer.

The compressed RGB Video stream is transferred from DSI Data lane to a Write Line Buffer. The RGB Data is shifted to a Read Line Buffer at the same time. Then the RGB data in the Read Line Buffer is transferred to a Display with Pixel Clock timing.

The benefit of this example is power saving over the DSI link. DSI Clock lane can be stopped and entered into Low Power Mode as well as DSI data lane.