Pixel Format and Pixel Clock

Figure 5 shows how to generate pixel clock from DSI clock or internal clock in each case of pixel format; 16-bit per pixel, 18-bit per pixel (Packed), 18-bit per pixel (loosely Packed), and 24-bit per pixel.

Pixel clock frequency is specified by Resolution and Frame rate of Display Panel. It may be specified independently from DSI clock rate. In this example, Pixel Clock is fixed to 3 Byte clock.

While RGB byte stream is written to Write Line Buffer by byte clock, RGB pixel data is read from Read Line Buffer by Pixel clock; i.e. 3 Byte clock. Therefore DSI data transmission is completed earlier than displaying the data in the case of 16-bit per pixel and 18-bit per pixel (Packed). In these cases, display timing is generated in the same manner as Burst Mode transmission.

Figure 5 Pixel format and Fixed Pixel Clock ( 3 Byte Clock) Example 

kjhcom@dgnte.com 

by MIPI Alliance
Display Working Group