Figure1
shows DSI Video Mode Interface Timing of Non-burst Communication with
sync event. When a peripheral receives H Sync Start packet followed
by HBP, it generates Hsync pulse. The pulse width of Hsync should
depend on a display spec. DE or Data Enable signal goes low when the
peripheral receives the first bit of Payload Data of RGB. DE goes
high when the peripheral receives the last bit of Payload Data of
RGB. The horizontal blanking time should be controlled by the period
of HBP and HFP; i.e. the Word Count of HBP Packet and HFP Packet.
Then the Valid Pixel Data duration is generated. Pixel Clock is
generated by the divided down DSI Clock. All these video mode timings
should be synchronous, because they are based on DSI Clock. In this
case, DSI Clock should be set to Free Running mode.
Figure
1 DSI Video Mode Interface Timing : Non-burst Communication Example
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