Welcome to MFG(Mipi Function Generator) World: 9월 2013

Pixel Format and Pixel Clock

Figure 5 shows how to generate pixel clock from DSI clock or internal clock in each case of pixel format; 16-bit per pixel, 18-bit per pixel (Packed), 18-bit per pixel (loosely Packed), and 24-bit per pixel.

Pixel clock frequency is specified by Resolution and Frame rate of Display Panel. It may be specified independently from DSI clock rate. In this example, Pixel Clock is fixed to 3 Byte clock.

While RGB byte stream is written to Write Line Buffer by byte clock, RGB pixel data is read from Read Line Buffer by Pixel clock; i.e. 3 Byte clock. Therefore DSI data transmission is completed earlier than displaying the data in the case of 16-bit per pixel and 18-bit per pixel (Packed). In these cases, display timing is generated in the same manner as Burst Mode transmission.

Figure 5 Pixel format and Fixed Pixel Clock ( 3 Byte Clock) Example

kjhcom@dgnte.com

by MIPI Alliance
Display Working Group

Video Mode Timing Generation

In this section, Video-Mode Timing examples are described to show how to generate video-mode timing signals from DSI data packets and DSI clock.

Figure 3 shows Display timing generation from DSI byte stream in Non-burst Mode.

Hsync, Vsync and Pixel clock signals need to be issued periodically and continuously in Video mode. Hsync signal should be generated after detecting ECC byte of HS sync packet. Hsync pulse width is defined by user system in this case; i.e. with sync event method ( See MIPI DSI specification, section 8.11.3 Non-Burst Mode with Sync Events).

DE timing “HACT” is determined by HBP and HFP, and specifies an effective display area. The duration of HACT shall be multiple of pixel clock period and HACT is determined by the number of horizontal pixel count. Since the end of DE timing is specified after detecting ECC of HFP packet, the start of DE timing should be delayed by 6 bytes including two checksum bytes of RGB Long packet. RGB long packet header and following 6 bytes data are included in HBP duration. And 4 bytes of HS short packet is included in HFP duration.

Figure 3 Display Timing Generation from DSI Byte Stream in Non-burst Mode

Figure 4 shows Display timing generation from DSI byte stream in Burst Mode. The main difference between Burst Mode and Non-burst Mode is existence of BLLP after transmitting compressed RGB data. To keep Hsync signal synchronous, the duration of BLLP shall be multiple of pixel clock period. In this case, HACT also represents effective display horizontal area. DE timing is different from Non-burst Mode case. The end timing of DE is the same as Non-burst Mode, but the start timing may be defined to the first byte of RGB payload data, because HACT time can be specified to adjust BLLP duration. Therefore, Host shall have the capability of adjusting BLLP time including EoT and SoT.

Figure 4 Display Timing Generation from DSI Byte Stream in Burst Mode

kjhcom@dgnte.com

by MIPI Alliance
Display Working Group

Burst Communication Example

Figure2 shows DSI Video Mode Interface Timing of Burst Communication with sync event. The generating method of Hsync and DE follows the same procedure of Non-burst Communication Example. In this case, there are two options for generating Pixel Clock. One is generated by the divided down DSI Clock and the other is the divided down Internal Clock in a peripheral.

When Internal Clock is used, Internal Clock or at least Pixel Clock should be synchronous with Hsync, otherwise the display data may not be shown on a display properly. DSI Clock may enter Low Power Mode during the BLLP time of DSI data lane as long as Internal Clock is operating. To achieve Burst Communication, line buffers or similar memories may be used. In this example two line buffers are used; Write Line Buffer and Read Line Buffer.

The compressed RGB Video stream is transferred from DSI Data lane to a Write Line Buffer. The RGB Data is shifted to a Read Line Buffer at the same time. Then the RGB data in the Read Line Buffer is transferred to a Display with Pixel Clock timing.

The benefit of this example is power saving over the DSI link. DSI Clock lane can be stopped and entered into Low Power Mode as well as DSI data lane.

Figure 2 DSI Video Mode Interface Timing : Burst Communication Example

kjhcom@dgnte.com

by MIPI Alliance
Display Working Group

Non-burst Communication Example

Figure1 shows DSI Video Mode Interface Timing of Non-burst Communication with sync event. When a peripheral receives H Sync Start packet followed by HBP, it generates Hsync pulse. The pulse width of Hsync should depend on a display spec. DE or Data Enable signal goes low when the peripheral receives the first bit of Payload Data of RGB. DE goes high when the peripheral receives the last bit of Payload Data of RGB. The horizontal blanking time should be controlled by the period of HBP and HFP; i.e. the Word Count of HBP Packet and HFP Packet. Then the Valid Pixel Data duration is generated. Pixel Clock is generated by the divided down DSI Clock. All these video mode timings should be synchronous, because they are based on DSI Clock. In this case, DSI Clock should be set to Free Running mode.