Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh)

Packed Pixel Stream 16-Bit Format is a Long packet used to transmit image data formatted as 16-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte checksum. Pixel format is five bits red, six bits green, five bits blue, in that order. Note that the “Green” component is split across two bytes. Within a color component, the LSB is sent first, the MSB last.

With this format, it is strongly recommended that TOTAL line width be a multiple of one pixel (two bytes) and that timing in the host display controller use that time unit for its activity, including assertion of Transmit Request to its PHY layer. This ensures that every scan line has the same synchronous relationship between the Byte clock and Pixel clock.

 Normally, the display has no frame buffer of its own, so all image data shall be supplied by the hostprocessor at a sufficiently high rate to avoid flicker or other visible artifacts.

Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh)

Packed Pixel Stream 18-Bit Format (Packed) is a Long packet. It is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. Pixel format is red (6 bits), green (6 bits) and blue (6 bits), in that order. Within a color component, the LSB is sent first, the MSB last.

Note that pixel boundaries only line up with byte boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent (width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. It is possible to send pixel data that represent a line width that is not a multiple of four pixels, but display logic on the receiver end shall dispose of the extra bits of the partial byte at the end of active display and ensure a “clean start” for the  next line.

Note that pixel boundaries only line up with byte boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent (width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. It is possible to send pixel data that represent a line width that is not a multiple of four pixels, but display logic on the receiver end shall dispose of the extra bits of the partial byte at the end of active display and ensure a “clean start” for the  next line.

Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh)

In the 18-bit Pixel Loosely Packed format, each R, G, or B color component is six bits but is shifted to the upper bits of the byte, such that the valid pixel bits occupy bits [7:2] of each byte. Bits [1:0] of each payload byte representing active pixels are ignored. As a result, each pixel requires three bytes as it is transmitted across the Link. This requires more bandwidth than the “packed” format, but requires less shifting and multiplexing logic in the packing and unpacking functions on each end of the Link.

This format is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (6 bits), green (6 bits) and blue (6 bits) in that order. Within a color component, the LSB is sent first, the MSB last.

With this format, pixel boundaries line up with byte boundaries every three bytes. It is strongly recommended that the total line width be a multiple of three bytes and that timing in the host processor use that time unit (three bytes) for its activity, including assertion of Transmit Request to its PHY layer. This ensures that every scan line has the same synchronous relationship between the Byte clock and Pixel clock.

Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh)

Packed Pixel Stream 24-Bit Format is a Long packet. It is used to transmit image data formatted as 24-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (8 bits), green (8 bits) and blue (8 bits), in that order. Each color component occupies one byte in the pixel stream; no components are split across byte boundaries. Within a color component, the LSB is sent first, the MSB last.

With this format, pixel boundaries line up with byte boundaries every three bytes. It is strongly recommended that the total line width be a multiple of three bytes and that timing in the host processor use that time unit (three bytes) for its activity, including assertion of Transmit Request to its PHY layer. This ensures that every scan line has the same synchronous relationship between the Byte clock and Pixel clock.

Summery for DSI

DSI is a Lane-scalable interface

• One Clock Lane
• One to Four Data Lanes

Transmission Mode

• High-Speed signaling mode (differential signal) (100mV~300mV)
• Low-Power signaling mode (single-ended signal) (0V~1.2V)  - For returning data, only use Data Lane 0 in LP Mode

Packet Types

• Short Packet：4 bytes (fixed length) - Data ID (1byte) + Data0 (1byte) + Data1 (1byte) + ECC (1byte)
• Long Packet：6~65541 bytes (variable length) - Packet Header (4 bytes) + Data Payload (0~65535 bytes) + Packet Footer (2 bytes)

Operation Mode
Command Mode (Similar to MPU IF)

• Automatic mode
• DSI PHY TE trigger
• CMOS TE line

Video Mode (Similar to RGB IF)

• Non-Burst Mode with Sync Pulses
• Non-Burst Mode with Sync Events
• Burst Mode

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Video Mode

DSI supports three formats for Video Mode data transmission

• Non-Burst Mode with Sync Pulses
• Non-Burst Mode with Sync Events
• Burst Mode

Non-Burst Mode with Sync Pulses

 With this format, the goal is to accurately convey DPI-type timing over the DSI serial Link. This includes matching DPI pixel-transmission rates, and widths of timing events like sync pulses. Accordingly, synchronization periods are defined using packets transmitting both start and end of sync pulses.

 

 Non-Burst Mode with Sync Events

This mode is a simplification of the format described Non-burst Mode with Sync  pulses. Only the start of each synchronization pulse is transmitted. The peripheral may regenerate sync pulses as needed from each Sync Event packet received. Pixels are transmitted at the same rate as they would in a corresponding parallel display interface such as DPI-2.

 Burst Mode

In this mode, blocks of pixel data can be transferred in a short time using a compressed burst format. This is a good strategy to reduce overall DSI power consumption, as well as enabling larger blocks of time for other data transmissions over the Link in either direction.

There may be a line buffer or similar memory on the peripheral to accommodate incoming data at high speed. Following HS pixel data transmission, the bus goes to Low Power Mode, during which it may remain idle, i.e. the host processor remains in LP-11 state, or LP transmission may take place in either direction. If the peripheral takes control of the bus for sending data to the host processor, its transmission time shall be limited to ensure data underflow does not occur from its internal buffer memory to the display device.

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Command Mode

A command mode display has its own timing controller and memory frame buffer. In order to avoid tearing effect it is needed to notify the host of timing events on the panel. The sending of the pixel data in a command mode can be achieved in 3 different manners:

•Automatic mode: The SW starts the transfer when it is needed by setting to the
                                      TE_START bit. TE_START is HW cleared once transfer is finished. It
                                       lets SW start the transfer  manually based on application events or
                                       based on the TE trigger interrupt. If no synchronization is done,
                                       then some tearing effect could appear.

• DSI PHY TE trigger: MIPI DSI standard defines a TE trigger message which is
                                         conveying from panel to host trough the DSI link. Once the
                                         trigger is received the pixel data is automatically started.

• CMOS TE line         : This synchronization method is not part of the MIPI DSI standard
                                          but it is supported by AP. The pixel data transfer will start
                                          automatically when the pre-defined event will happen on the TE
                                          CMOS line.

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Data Lanes HS Transmission Example(1~4 Lanes)

One-Data Lane Configuration

Two-Data Lane Configuration

Three-Data Lane Configuration

Four-Data Lane Configuration

Multiple Packets per Transmission

In its simplest form, a transmission may contain one packet. If many packets are to be transmitted, the overhead of frequent switching between LPS and High-Speed Mode will severely limit bandwidth if packets are sent separately, e.g. one packet per transmission.

Separate Transmissions

single Transmission

KEY:

• LPS – Low Power State                     
• SP – Short Packet
• SoT – Start of Transmission            
• LgP – Long Packet
• EoT – End of Transmission

Short Packet Structure

Packet Header (4 bytes)

• Data Identifier (DI) * 1byte： Contains the Virtual Channel[7:6] and Data Type[5:0].
• Packet Data * 2byte：Length is fixed at two bytes
• Error Correction Code (ECC) * 1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.

Packet Size

• Fixed length 4 bytes

The first byte of any packet is the DI (Data Identifier) byte.

• DI[7:6]：These two bits identify the data as directed to one of four virtual channels.
• DI[5:0]：These six bits specify the Data Type.

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Long Packet Structure

Packet Header (4 bytes)

• Data Identifier (DI) * 1byte：Contains the Virtual Channel[7:6] and Data Type[5:0].
• Word Count (WC) * 2byte：defines the number of bytes in the Data Payload.
• Error Correction Code (ECC) * 1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.

Data Payload (0~65535 bytes)

• Length = WC × bytes

Packet Footer (2 bytes)：Checksum

• If the payload has length 0, then the Checksum calculation results in FFFFh
• If the Checksum isn’t calculated, the Checksum value is 0000h

Packet Size

• 4 + (0~65535) + 2 = 6 ~ 65541 bytes

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Data Types for Processor-sourced Packets

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Error Correction Code

 P7 = 0
 P6 = 0
 P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23
 P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23
 P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23
 P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22
 P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23
 P0 = D0^D1^D2^D4^D5^D7^D10^D11^D13^D16^D20^D21^D22^D23

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Checksum

unsigned char xx[] = {0x01,0x5a,0x5a,0x03,0x08,0x2A, 0x00,0x01
                                          ,0x00,0xF8,0x00,0xF6,0x57,0x00,0X00,0xE5};

typedef unsigned short  U16;
typedef unsigned char   U8;

U16 CRC_kjh;
U16 crc16_update(U16 crc, U8 a);

int main()
{
            U16 crc,k;
            crc = 0xFFFF;
            for (k=0; k<1; k++) crc = crc16_update(crc, xx[k]);
            CRC_kjh = crc;
}

U16 crc16_update(U16 crc, U8 a)
{
            int j;
            crc ^=a;
                        for (j = 0; j < 8; ++j)
                       {
                              if (crc & 1) crc = (crc >> 1) ^ 0x8408;
                              else crc = (crc >> 1);
                       }
             return crc;
}

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Data type for Peripheral-to-Processor LP Transmissions

Detailed format description

• Packet structure for peripheral-to-processor transactions is the same as for
• the processor-to-peripheral direction

 For a single-byte read response, valid data shall be returned in the first byte The second byte shall be sent as 00h

If the peripheral does not support Checksum it shall return 0000h

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Peripheral-to-Processor LP Transmissions

Peripheral-to-processor transactions are of four basic types

• Tearing Effect (TE)：trigger message (BAh)
• Acknowledge：trigger message (84h)
• Acknowledge and Error Report：short packet (Data Type is 02h)
• Response to Read Request：short packet or long packet - Generic Read Response、DCS Read Response（1byte, 2byte, multi byte）

Feature

• BTA shall take place after every peripheral-to-processor transaction 
• Multi-Lane systems shall use Lane 0 for all peripheral-to-processor transmissions
• Reverse-direction signaling shall only use LP mode of transmission

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